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UPI-41AH 42AH UNIVERSAL PERIPHERAL INTERFACE 8-BIT SLAVE MICROCONTROLLER
Y Y
UPI-41 6 MHz UPI-42 12 5 MHz Pin Software and Architecturally Compatible with all UPI-41 and UPI-42 Products 8-Bit CPU plus ROM OTP EPROM RAM I O Timer Counter and Clock in a Single Package 2048 x 8 ROM OTP 256 x 8 RAM on UPI-42 1024 x 8 ROM OTP 128 x 8 RAM on UPI-41 8-Bit Timer Counter 18 Programmable I O Pins One 8-Bit Status and Two Data Registers for Asynchronous Slave-toMaster Interface DMA Interrupt or Polled Operation Supported
Y
Fully Compatible with all Intel and Most Other Microprocessor Families Interchangeable ROM and OTP EPROM Versions Expandable I O Sync Mode Available Over 90 Instructions 70% Single Byte Available in EXPRESS Standard Temperature Range inteligent Programming Algorithm Fast OTP Programming Available in 40-Lead Plastic and 44Lead Plastic Leaded Chip Carrier Packages
(See Packaging Spec Order Package Type P and N 240800-001)
Y
Y
Y Y Y
Y
Y
Y
Y
Y
Y
The Intel UPI-41AH and UPI-42AH are general-purpose Universal Peripheral Interfaces that allow the designer to develop customized solutions for peripheral device control They are essentially ``slave'' microcontrollers or microcontrollers with a slave interface included on the chip Interface registers are included to enable the UPI device to function as a slave peripheral controller in the MCS Modules and iAPX family as well as other 8- 16- and 32-bit systems To allow full user flexibility the program memory is available in ROM and One-Time Programmable EPROM (OTP) All UPI-41AH and UPI-42AH devices are fully pin compatible for easy transition from prototype to production level designs
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Figure 1 DIP Pin Configuration
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Figure 2 PLCC Pin Configuration
November 1994
Order Number 210393-008
UPI-41AH 42AH
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Figure 3 Block Diagram
UPI PRODUCT MATRIX
UPI Device 8042AH 8242AH 8742AH 8041AH 8741AH 1K 1K ROM 2K 2K 2K OTP EPROM RAM 256 256 256 128 128 12 5V 12 5V Programming Voltage
THE INTEL 8242
As shown in the UPI-42 product matrix the UPI-42 will be offered as a pre-programmed 8042 with several software vendors' keyboard controller firmware The current list of available 8242 versions include keyboard controller firmware from both Phoenix Technologies Ltd IBM and Award Software Inc The 8242 is programmed with Phoenix Technologies Ltd keyboard controller firmware for AT-compatible systems This keyboard controller is fully compatible with all AT-compatible operating systems and applications The 8242PC also contains Phoenix Technologies Ltd firmware This keyboard controller
provides support for AT PS 2 and most EISA platforms as well as PS 2-style mouse support for either AT or PS 2 platforms The Intel 8242BB is programmed with IBM's keyboard controller firmware The 8242BB provides an off the shelf keyboard and auxiliary device controller for AT PS 2 EISA and PCI architectures The 8242WA contains Award Software Inc firmware This device provides at AT-compatible keyboard controller for use in IBM PC AT compatible computers The 8242WB contains a version of Award Software Inc firmware that provides PS 2 style mouse support in addition to the standard features of the 8242WA
Contact factory for current code revision available in all versions of the 8242 product lines
2
UPI-41AH 42AH
Table 1 Pin Description
Symbol DIP Pin No 1 39 PLCC Pin Type No 2 43 I Name and Function
TEST 0 TEST 1
TEST INPUTS Input pins which can be directly tested using conditional branch instructions FREQUENCY REFERENCE TEST 1 (T1) also functions as the event timer input (under software control) TEST 0 (T0) is used during PROM programming and ROM EPROM verification It is also used during Sync Mode to reset the instruction state to S1 and synchronize the internal clock to PH1 See the Sync Mode Section INPUTS Inputs for a crystal LC or an external timing signal to determine the internal oscillator frequency RESET Input used to reset status flip-flops and to set the program counter to zero RESET is also used during EPROM programming and verification SINGLE STEP Single step input used in conjunction with the SYNC output to step the program through each instruction (EPROM) This should be tied to a 5V when not used This pin is also used to put the device in Sync Mode by applying 12 5V to it CHIP SELECT Chip select input used to select one UPI microcomputer out of several connected to a common data bus EXTERNAL ACCESS External access input which allows emulation testing and ROM EPROM verification This pin should be tied low if unused READ I O read input which enables the master CPU to read data and status words from the OUTPUT DATA BUS BUFFER or status register COMMAND DATA SELECT Address Input used by the master processor to indicate whether byte transfer is data (A0 e 0 F1 is reset) or command (A0 e 1 F1 is set) A0 e 0 during program and verify operations WRITE I O write input which enables the master CPU to write data and command words to the UPI INPUT DATA BUS BUFFER OUTPUT CLOCK Output signal which occurs once per UPI instruction cycle SYNC can be used as a strobe for external circuitry it is also used to synchronize single step operation DATA BUS Three-state bidirectional DATA BUS BUFFER lines used to interface the UPI microcomputer to an 8-bit master system data bus PORT 1 8-bit PORT 1 quasi-bidirectional I O lines P10 -P17 access the signature row and security bit PORT 2 8-bit PORT 2 quasi-bidirectional I O lines The lower 4 bits (P20 -P23) interface directly to the 8243 I O expander device and contain address and data information during PORT 4-7 access The upper 4 bits (P24 -P27) can be programmed to provide interrupt Request and DMA Handshake capability Software control can configure P24 as Output Buffer Full (OBF) interrupt P25 as Input Buffer Full (IBF) interrupt P26 as DMA Request (DRQ) and P27 as DMA ACKnowledge (DACK) PROGRAM Multifunction pin used as the program pulse input during PROM programming During I O expander access the PROG pin acts as an address data strobe to the 8243 This pin should be tied high if unused POWER a 5V main power supply pin POWER a 5V during normal operation a 12 5V during programming operation Low power standby supply pin GROUND Circuit ground potential
XTAL 1 XTAL 2 RESET SS
2 3 4 5
3 4 5 6
I I I
CS EA RD A0
6 7 8 9
7 8 9 10
I I I I
WR SYNC
10 11
11 13
I O
D0 - D7 (BUS)
12 - 19 14- 21
IO IO IO
P10 - P17 27 - 34 30- 33 35- 38 P20 - P27 21 - 24 24- 27 35 - 38 39- 42
PROG
25
28
IO
VCC VDD VSS
40 26 20
44 29 22
3
UPI-41AH 42AH
During the time that the host CPU is reading the status register the UPI is prevented from updating this register or is `locked out ' 4 P24 and P25 are port pins or Buffer Flag pins which can be used to interrupt a master processor These pins default to port pins on Reset If the ``EN FLAGS'' instruction has been executed P24 becomes the OBF (Output Buffer Full) pin A ``1'' written to P24 enables the OBF pin (the pin outputs the OBF Status Bit) A ``0'' written to P24 disables the OBF pin (the pin remains low) This pin can be used to indicate that valid data is available from the UPI (in Output Data Bus Buffer) If ``EN FLAGS'' has been executed P25 becomes the IBF (Input Buffer Full) pin A ``1'' written to P25 enables the IBF pin (the pin outputs the inverse of the IBF Status Bit A ``0'' written to P25 disables the IBF pin (the pin remains low) This pin can be used to indicate that the UPI is ready for data
UPI-41AH and UPI-42AH FEATURES
1 Two Data Bus Buffers one for input and one for output This allows a much cleaner Master Slave protocol
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2 8 Bits of Status ST7 ST6 ST5 ST4 F1 F0 IBF OBF D7 D6 D5 D4 D3 D2 D1 D0 ST4 -ST7 are user definable status bits These bits are defined by the ``MOV STS A'' single byte single cycle instruction Bits 4-7 of the acccumulator are moved to bits 4-7 of the status register Bits 0-3 of the status register are not affected
MOV STS A Op Code 90H
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1
0
0
1
0
0
0
0 Data Bus Buffer Interrupt Capability
EN FLAGS Op Code 0F5H
D7 D0 3 RD and WR are edge triggered IBF OBF F1 and INT change internally after the trailing edge of RD or WR
1 D7
1
1
1
0
1
0
1 D0
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4
UPI-41AH 42AH
5 P26 and P27 are port pins or DMA handshake pins for use with a DMA controller These pins default to port pins on Reset If the ``EN DMA'' instruction has been executed P26 becomes the DRQ (DMA Request) pin A ``1'' written to P26 causes a DMA request (DRQ is activated) DRQ is deactivated by DACKRD DACKWR or execution of the ``EN DMA'' instruction If ``EN DMA'' has been executed P27 becomes the DACK (DMA ACKnowledge) pin This pin acts as a chip select input for the Data Bus Buffer registers during DMA transfers
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Figure 5 8088-UPI-41AH 42AH Interface
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DMA Handshake Capability
EN DMA Op Code 0E5H
Figure 6 8048H-UPI-41 42 Interface
1
1
1
0
0
1
0
1
D7 D0 6 When EA is enabled on the UPI the program counter is placed on Port 1 and the lower three bits of Port 2 (MSB e P22 LSB e P10) On the UPI this information is multiplexed with PORT DATA (see port timing diagrams at end of this data sheet) 7 The 8741AH and 8742AH support the inteligent Programming Algorithm (See the Programming Section )
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Figure 7 UPI-41 42-8243 Keyboard Scanner
APPLICATIONS
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Figure 4 UPI-41AH 42AH Keyboard Controller 5
UPI-41AH 42AH
The Program Verify sequence is 1 CS e 5V VCC e 5V VDD e 5V RESET e 0V A0 e 0V TEST 0 e 5V clock applied or internal oscillator operating BUS floating PROG e 5V 2 Insert 8741AH or 8742AH in programming socket 3 TEST 0 e 0V (select program mode) 4 EA e 12 5V (active program mode) 5 VCC e 6V (programming supply) 6 VDD e 12 5V (programming power) 7 Address applied to BUS and P20-22 8 RESET e 5V (latch address) 9 Data applied to BUS 10 PROG e 5V followed by one 1 ms pulse to 0V 11 TEST 0 e 5V (verify mode)
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Figure 8 UPI-41AH 42AH 80-Column Matrix Printer Interface
12 Read and verify data on BUS 13 TEST 0 e 0V 14 Apply overprogram pulse 15 RESET e 0V and repeat from step 6 16 Programmer should be at conditions of step 1 when 8741AH or 8742AH is removed from socket Please follow the inteligent Programming flow chart for proper programming procedure
PROGRAMMING AND VERIFYING THE 8741AH AND 8742AH OTP EPROM Programming Verification
In brief the programming process consists of activating the program mode applying an address latching the address applying data and applying a programming pulse Each word is programmed completely before moving on to the next and is followed by a verification step The following is a list of the pins used for programming and a description of their functions Pin XTAL 1 Reset Test 0 EA BUS P20-22 VDD PROG 2 Clock Inputs Initialization and Address Latching Selection of Program or Verify Mode Activation of Program Verify Signature Row Security Bit Modes Address and Data Input Data Output During Verify Address Input Programming Power Supply Program Pulse Input Function
inteligent Programming Algorithm
The inteligent Programming Algorithm rapidly programs Intel 8741AH 8742AH EPROMs using an efficient and reliable method particularly suited to the production programming environment Typical programming time for individual devices is on the order of 10 seconds Programming reliability is also ensured as the incremental program margin of each byte is continually monitored to determine when it has been successfully programmed A flowchart of the 8741AH 8742AH inteligent Programming Algorithm is shown in Figure 9 The inteligent Programming Algorithm utilizes two different pulse types initial and overprogram The duration of the initial PROG pulse(s) is one millisecond which will then be followed by a longer overprogram pulse of length 3X msec X is an iteration counter and is equal to the number of the initial one millisecond pulses applied to a particular 8741AH 8742AH location before a correct verify occurs Up to 25 one-millisecond pulses per byte are provided for before the overprogram pulse is applied
WARNING An attempt to program a missocketed 8741AH or 8742AH will result in severe damage to the part An indication of a properly socketed part is the appearance of the SYNC clock output The lack of this clock may be used to disable the programmer
6
UPI-41AH 42AH
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Figure 9 Programming Algorithm
7
UPI-41AH 42AH
The entire sequence of program pulses and byte verifications is performed at VCC e 6 0V and VDD e 12 5V When the inteligent Programming cycle has been completed all bytes should be compared to the original data with VCC e 5 0 VDD e 5V b Apply access code to appropriate inputs to put the device into security mode c Apply high voltage to EA and VDD pins d Follow the programming procedure as per the inteligent Programming Algorithm with known data on the databus Not only the security bit but also the security byte of the signature row is programmed e Verify that the security byte of the signature mode contains the same data as appeared on the data bus (If DB0 - DB7 e high the security byte will contain FFH ) f Read two consecutive known bytes from the EPROM array and verify that the wrong data are retrieved in at least one verification If the EPROM can still be read the security bit may have not been fully programmed though the security byte in the signature mode has
Verify
A verify should be performed on the programmed bits to determine that they have been correctly programmed The verify is performed with T0 e 5V VDD e 5V EA e 12 5V SS e 5V PROG e 5V A0 e 0V and CS e 5V
SECURITY BIT
The security bit is a single EPROM cell outside the EPROM array The user can program this bit with the appropriate access code and the normal programming procedure to inhibit any external access to the EPROM contents Thus the user's resident program is protected There is no direct external access to this bit However the security byte in the signature row has the same address and can be used to check indirectly whether the security bit has been programmed or not The security bit has no effect on the signature mode so the security byte can always be examined
Verification
Since the security bit address overlaps the address of the security byte of the signature mode it can be used to check indirectly whether the security bit has been programmed or not Therefore the security bit verification is a mere read operation of the security byte of the signature row (0FFH e security bit programmed 00H e security bit unprogrammed) Note that during the security bit programming the reading of the security byte does not necessarily indicate that the security bit has been successfully programmed Thus it is recommended that two consecutive known bytes in the EPROM array be read and the wrong data should be read at least once because it is highly improbable that random data coincides with the correct ones twice
SECURITY BIT PROGRAMMING VERIFICATION Programming
a Read the security byte of the signature mode Make sure it is 00H
8
UPI-41AH 42AH
The code is 43H and 42H for the 8042AH and OTP 8742AH and 41H and 40H for the 8041AH and OTP 8741AH respectively The code is 44H for any device with the security bit set by Intel C User signature The user signature memory is implemented in the EPROM and consists of 2 bytes for the customer to program his own signature code (for identification purposes and quick sorting of previously programmed materials) D Test signature This memory is used to store testing information such as test data bin number etc (for use in quality and manufacturing control) E Security byte This byte is used to check whether the security bit has been programmed (see the security bit section)
SIGNATURE MODE
The UPI-41AH 42AH has an additional 32 bytes of EPROM available for Intel and user signatures and miscellaneous purposes The 32 bytes are partitioned as follows A Test code checksum This can accommodate up to 25 bytes of code for testing the internal nodes that are not testable by executing from the external memory The test code checksum is present on ROMs and OTPs B Intel signature This allows the programmer to read from the UPI-41AH 42AH the manufacturer of the device and the exact product name It facilitates automatic device identification and will be present in the ROM and OTP versions Location 10H contains the manufacturer code For Intel it is 89H Location 11H contains the device code
The signature mode can be accessed by setting P10 e 0 P11 - P17 e 1 and then following the programming and or verification procedures The location of the various address partitions are as follows Device Type 0FH 1EH 11H 13H 15H ROM OTP ROM OTP OTP ROM OTP OTP No of Bytes 25 2 2 2 1
Address Test Code Checksum Intel Signature User Signature Test Signature Security Byte 0 16H 10H 12H 14H 1FH
9
UPI-41AH 42AH
Sync Mode is enabled when SS pin is raised to high voltage level of a 12 volts To begin synchronization T0 is raised to 5 volts at least four clock cycles after SS T0 must be high for at least four X1 clock cycles to fully reset the prescaler and time state generators T0 may then be brought down during low state of X1 Two clock cycles later with the rising edge of X1 the device enters into Time State 1 Phase 1 SS is then brought down to 5 volts 4 clocks later after T0 RESET is allowed to go high 5 tCY (75 clocks) later for normal execution of code
SYNC MODE
The Sync Mode is provided to ease the design of multiple controller circuits by allowing the designer to force the device into known phase and state time The Sync Mode may also be utilized by automatic test equipment (ATE) for quick easy and efficient synchronizing between the tester and the DUT (device under test)
SYNC MODE TIMING DIAGRAMS
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Minimum Specifications SYNC Operation Time tSYNC e 3 5 XTAL 1 Clock cycles Reset Time tRS e 4 tCY NOTE The rising and falling edges of T0 should occur during low state of XTAL1 clock
10
UPI-41AH 42AH
ACCESS CODE
The following table summarizes the access codes required to invoke the Sync Mode Signature Mode and the Security Bit respectively Also the programming and verification modes are included for comparison
Control Signals T0 RST SS EA PROG VDD VCC 0 Programming Mode Verification Mode Sync Mode Signature Prog Mode Verify Security Bit Byte Prog Verify 0 0 0 1 STB High 0 0 0 1 0 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 1 HV 1 HV 1 HV 1 HV HV 0 1 HV 1 HV 1 HV 1 HV 1 HV 1 HV 1 HV 1 HV 1 STB 1 1 X 1 STB 1 1 1 STB 1 1 VDDH VCC VDDH VCC VCC VCC VCC VCC VCC VCC X VDDH VCC VDDH VCC VCC VCC VCC VCC VDDH VCC VDDH VCC VCC VCC VCC VCC X X 1 2 Data Bus 3 4 5 6 7 Access Code Port 2 Port 1
Modes
012 0 1 234567 Addr Addr Addr Addr a0 a1 X X X X X X a0 a1 X X X X X X
Address Data In Address Data Out X X X X
X XXX X X XXXXXX 0 0 0 0 1 1 1 1XX1 000 000 000 000 000 000 000
Addr (see Sig Mode Table) Data In Addr (see Sig Mode Table) Data Out Address Data In Address Data Out
NOTES 1 a0 e 0 or 1 a1 e 0 or 1 a0 must e a1
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature Under Bias 0 C to a 70 C b 65 C to a 150 C Storage Temperature Voltage on Any Pin with b 0 5V to a 7V Respect to Ground Power Dissipation 15W
NOTICE This is a production data sheet The specifications are subject to change without notice
WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability
D C CHARACTERISTICS
Symbol VIL VIL1 VIH VIH1 VIH2 VOL
TA e 0 C to a 70 C VCC e VDD e a 5V g10% UPI-41AH 42AH Min Max 08 06 VCC VCC VCC 0 45 V V V V V V IOL e 2 0 mA Units Notes
Parameter Input Low Voltage (Except XTAL1 XTAL2 RESET) Input Low Voltage (XTAL1 XTAL2 RESET) Input High Voltage (Except XTAL1 XTAL2 RESET) Input High Voltage (XTAL1 RESET) Input High Voltage (XTAL2) Output Low Voltage (D0 -D7)
b0 5 b0 5
20 35 22
11
UPI-41AH 42AH
D C CHARACTERISTICS
Symbol VOL1 VOL2 VOH VOH1 IIL IOFL ILI ILI1 IDD ICC a IDD IIH CIN CIO
TA e 0 C to a 70 C VCC e VDD e a 5V g10% (Continued) Parameter UPI-41AH 42AH Min Max 0 45 0 45 24 24
g10 g10
Units V V V
Notes IOL e 1 6 mA IOL e 1 0 mA IOH e b 400 mA IOH e b 50 mA
Output Low Voltage (P10P17 P20P27 Sync) Output Low Voltage (PROG) Output High Voltage (D0 -D7) Output High Voltage (All Other Outputs) Input Leakage Current (T0 T1 RD WR CS A0 EA) Output Leakage Current (D0 -D7 High Z State) Low Input Load Current (P10P17 P20P27) Low Input Load Current (RESET SS) VDD Supply Current Total Supply Current
mA VSS s VIN s VCC mA VSS a 0 45 s VOUT s VCC mA VIL e 0 8V mA VIL e 0 8V mA Typical e 8 mA mA Typical e 80 mA mA Typical e 8 mA mA VIN e VCC pF pF TA e 25 C (1) TA e 25 C (1)
03 02 20 135 20 100 10 20
IDD Standby Power Down Supply Current Input Leakage Current (P10 -P17 P20 -P27) Input Capacitance I O Capacitance
NOTE 1 Sampled not 100% tested
D C CHARACTERISTICS
Symbol VDDH VDDL VPH VPL VEAH VEAL IDD IEA
PROGRAMMING
Parameter Min 12 4 75 20
b0 5
TA e 25 C g5 C VCC e 6V g0 25V VDD e 12 5V g0 5V Max 13 5 25 55 08 13 0 5 25 50 0 10 Units V(1) V V V V(2) V mA mA
VDD Program Voltage High Level VDD Voltage Low Level PROG Program Voltage High Level PROG Voltage Low Level Input High Voltage for EA EA Voltage Low Level VDD High Voltage Supply Current EA High Voltage Supply Current
12 0
b0 5
NOTES 1 Voltages over 13V applied to pin VDD will permanently damage the device 2 VEAH must be applied to EA before VDDH and removed after VDDL 3 VCC must be applied simultaneously or before VDD and must be removed simultaneously or after VDD
12
UPI-41AH 42AH
A C CHARACTERISTICS
DBB READ Symbol tAR tRA tRR tAD tRD tDF DBB WRITE Symbol tAW tWA tWW tDW tWD CLOCK Symbol tCY (UPI-41AH 42AH) tCYC (UPI-41AH 42AH) tPWH tPWL tR tF
NOTE 1 tCY e 15 f(XTAL)
TA e 0 C to a 70 C VSS e 0V VCC e VDD e a 5V g10%
Parameter CS A0 Setup to RDv CS A0 Hold After RDu RD Pulse Width CS A0 to Data Out Delay RDv to Data Out Delay RDu to Data Float Delay
Min 0 0 160
Max
Units ns ns ns
130 0 130 85
ns ns ns
Parameter CS A0 Setup to WRv CS A0 Hold After WRu WR Pulse Width Data Setup to WRu Data Hold After WRu
Min 0 0 160 130 0
Max
Units ns ns ns ns ns
Parameter Cycle Time Clock Period Clock High Time Clock Low Time Clock Rise Time Clock Fall Time
Min 12 80 30 30
Max 9 20 613
Units ms(1) ns ns ns
10 10
ns ns
A C CHARACTERISTICS
Symbol tACC tCAC tACD tCRQ
NOTE 1 CL e 150 pF
DMA Parameter Min 0 0 0 130 110 Max Units ns ns ns ns(1)
DACK to WR or RD RD or WR to DACK DACK to Data Valid RD or WR to DRQ Cleared
13
UPI-41AH 42AH
A C CHARACTERISTICS
PROGRAMMING
TA e 25 C g5 C VCC e 6V g0 25V VDDL e a 5V g0 25V VDDH e 12 5V g0 5V (8741AH 8742AH ONLY) Symbol tAW tWA tDW tWD tPW tTW tWT tDO tWW tr tf tCY tRE tOPW tDE Parameter Address Setup Time to RESETu Address Hold Time After RESETu Data in Setup Time to PROGv Data in Hold Time After PROGu Initial Program Pulse Width Test 0 Setup Time for Program Mode Test 0 Hold Time After Program Mode Test 0 to Data Out Delay RESET Pulse Width to Latch Address PROG Rise and Fall Times CPU Operation Cycle Time RESET Setup Time Before EAu Overprogram Pulse Width EA High to VDD High 4tCY 05 25 4tCY 2 85 1tCY 78 75 ms(2) 100 3 75 ms ms Min 4tCY 4tCY 4tCY 4tCY 0 95 4tCY 4tCY 4tCY 1 05 ms(1) Max Units
NOTES 1 Typical Initial Program Pulse width tolerance e 1 ms g5% 2 This variation is a function of the iteration counter value X 3 If TEST 0 is high tDO can be triggered by RESETu
A C CHARACTERISTICS
Symbol tCP tPC tPR tPF tDP tPD tPP
PORT 2 TA e 0 C to a 70 C VCC e a 5V g10% f(tCY)(3) 1 15 tCY b 28 1 10 tCY 8 15 tCY b 16 0 2 10 tCY 1 10 tCY b 80 6 10 tCY 250 45 750 Min 55 125 650 150 Max Units ns(1) ns(2) ns(1) ns(2) ns(1) ns(2) ns
Parameter Port Control Setup Before Falling Edge of PROG Port Control Hold After Falling Edge of PROG PROG to Time P2 Input Must Be Valid Input Data Hold Time Output Data Setup Time Output Data Hold Time PROG Pulse Width
NOTES 1 CL e 80 pF 2 CL e 20 pF 3 tCY e 1 25 ms
14
UPI-41AH 42AH
A C TESTING INPUT OUTPUT WAVEFORM
INPUT OUTPUT
A C TESTING LOAD CIRCUIT
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DRIVING FROM EXTERNAL SOURCE-TWO OPTIONS
l 6 MHz
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Rise and Fall Times Should Not Exceed 10 ns Resistors to VCC are Needed to Ensure VIH e 3 5V if TTL Circuitry is Used
LC OSCILLATOR MODE
CRYSTAL OSCILLATOR MODE
L C NOMINAL 45 H 20 pF 5 2 MHz 120 H 20 pF 3 2 MHz
fe
1 2q0LC C a 3Cpp 2 C1 C2 C3
Ce
Cpp j 5- 10 pF Pin-to-Pin Capacitance 210393 - 18 Each C Should be Approximately 20 pF including Stray Capacitance
210393 - 19 5 pF (STRAY 5 pF) (CRYSTAL a STRAY) 8 pF 20 - 30 pF INCLUDING STRAY
Crystal Series Resistance Should be Less Than 30X at 12 5 MHz
15
UPI-41AH 42AH
WAVEFORMS
READ OPERATION DATA BUS BUFFER REGISTER
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WRITE OPERATION
DATA BUS BUFFER REGISTER
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CLOCK TIMING
210393 - 22
16
UPI-41AH 42AH
WAVEFORMS (Continued)
COMBINATION PROGRAM VERIFY MODE
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NOTES 1 A0 must be held low (0V) during program verify modes 2 For VIH VIH1 VIL VIL1 VDDH and VDDL please consult the D C Characteristics Table 3 When programming the 8741AH 8742AH a 0 1 mF capacitor is required across VDD and ground to suppress spurious voltage transients which can damage the device
VERIFY MODE
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NOTES 1 PROG must float if EA is low 2 PROG must float or e 5V when EA is high 3 P10 - P17 e 5V or must float 4 P24 - P27 e 5V or must float 5 A0 must be held low during programming verify modes
17
UPI-41AH 42AH
WAVEFORMS (Continued)
DMA
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PORT 2
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PORT TIMING DURING EXTERNAL ACCESS (EA)
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On the Rising Edge of SYNC and EA is Enabled Port Data is Valid and can be Strobed On the Trailing Edge of Sync the Program Counter Contents are Available
18
UPI-41AH 42AH
Table 2 UPI Instruction Set
Mnemonic Description Bytes 1 1 2 1 1 2 1 1 2 1 1 2 1 1 2 1 1 1 1 1 1 1 1 1 1 Cycles 1 1 2 1 1 MOV Rr 2 1 1 2 1 1 2 1 1 MOVP3 A 2 1 1 1 1 1 1 1 1 1 1 A MOV Rr data MOV A PSW MOV PSW A XCH A Rr XCH A XCHD A MOVP A Rr Rr A data Mnemonic DATA MOVES MOV A Rr MOV A Rr MOV A data MOV Rr A MOV Rr A Description Move register to A Move data memory to A Move immediate to A Move A to register Move A to data memory Move immediate to register Move immediate to data memory Move PSW to A Move A to PSW Exchange A and register Exchange A and data memory Exchange digit of A and register Move to A from current page Move to A from page 3 Bytes 1 1 2 1 1 2 2 1 1 1 1 1 1 1 Cycles 1 1 2 1 1 2 2 1 1 1 1 1 2 2 ACCUMULATOR ADD A Rr Add register to A Add data memory ADD A Rr to A Add immediate to A ADD A data ADDC A Rr Add register to A with carry Add data memory ADDC A Rr to A with carry ADDC A data Add immediate to A with carry ANL A Rr AND register to A AND data memory ANL A Rr to A ANL A data AND immediate to A ORL A Rr OR register to A OR data memory ORL A Rr to A OR immediate to A ORL A data XRL A Rr Exclusive OR register to A Exclusive OR data XRL A Rr memory to A Exclusive OR immeXRL A data diate to A INC A Increment A DEC A Decrement A CLR A Clear A CPL A Complement A DA A Decimal Adjust A SWAP A Swap nibbles of A RL A Rotate A left RLC A Rotate A left through carry RR A Rotate A right RRC A Rotate A right through carry INPUT OUTPUT IN A Pp Input port to A OUTL Pp A Output A to port ANL Pp data AND immediate to port ORL Pp data OR immediate to port IN A DBB Input DBB to A clear IBF OUT DBB A Output A to DBB set OBF MOV STS A A4 - A7 to Bits 4-7 of Status MOVD A Pp Input Expander port to A MOVD Pp A Output A to Expander port ANLD Pp A AND A to Expander port ORLD Pp A OR A to Expander port
TIMER COUNTER MOV A T Read Timer Counter MOV T A Load Timer Counter STRT T Start Timer STRT CNT Start Counter STOP TCNT Stop Timer Counter EN TCNTI Enable Timer Counter Interrupt DIS TCNTI Disable Timer Counter Interrupt CONTROL EN DMA EN I DIS I EN FLAGS SEL RB0 SEL RB1 NOP REGISTERS INC Rr INC Rr DEC Rr Enable DMA Handshake Lines Enable IBF Interrupt Diable IBF Interrupt Enable Master Interrupts Select register bank 0 Select register bank 1 No Operation Increment register Increment data memory Decrement register
1 1 1 1 1 1 1
1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
1 1 2 2 1 1 1 1 1 1 1
2 2 2 2 1 1 1 2 2 2 2
19
UPI-41AH 42AH
Table 2 UPI Instruction Set (Continued)
Mnemonic SUBROUTINE CALL addr RET RETR FLAGS CLR C CPL C CLR F0 CPL F0 CLR F1 CPL F1 BRANCH JMP addr JMPP A DJNZ Rr addr JC addr JNC addr JZ addr JNZ addr JT0 addr JNT0 addr JT1 addr JNT1 addr JF0 addr JF1 addr JTF addr JNIBF addr JOBF addr JBb addr Description Jump to subroutine Return Return and restore status Clear Carry Complement Carry Clear Flag 0 Complement Flag 0 Clear F1 Flag Complement F1 Flag Jump unconditional Jump indirect Decrement register and jump Jump on Carry e 1 Jump on Carry e 0 Jump on A Zero Jump on A not Zero Jump on T0 e 1 Jump on T0 e 0 Jump on T1 e 1 Jump on T1 e 0 Jump on F0 Flag e 1 Jump on F1 Flag e 1 Jump on Timer Flag e 1 Clear Flag Jump on IBF Flag e0 Jump on OBF Flag e1 Jump on Accumulafor Bit Bytes 2 1 1 Cycles 2 2 2
1 1 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
INTEL CORPORATION 2200 Mission College Blvd Santa Clara CA 95052 Tel (408) 765-8080 INTEL CORPORATION (U K ) Ltd Swindon United Kingdom Tel (0793) 696 000 INTEL JAPAN k k Ibaraki-ken Tel 029747-8511
Printed in U S A xxxx 1196 B10M xx xx

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